1. Field of the Invention
The present invention relates to an input buffer circuit, and in particular to an input buffer circuit which can compensate for a data hold time and reduce an operational current.
2. Description of the Background Art
FIG. 1 is a circuit diagram illustrating a conventional input buffer circuit 5. Referring to FIG. 1, the input buffer circuit 5 includes: a NOR gate NOR1 NORing a data signal DIN inputted to a data input pad and a control signal WECS into which an enable signal WE and a chip selection signal CS are combined; and a delay unit 1, having first to n-th inverters INV1.about.INVn delaying an output signal from the NOR gate NOR 1.
The first inverter INV1 of the delay unit 1 includes: first and second PMOS transistors PM1, PM2 and first and second NMOS transistors NM1, NM2 connected in series between an external power voltage VCC and a ground voltage VSS. The gates of PM1, PM2, NM1 and NM2 are commonly connected to form an input terminal receiving an output signal from the NOR gate NOR1, and drains of the second PMOS transistor PM2 and the first NMOS transistor NM1 are commonly connected to form an output terminal outputting an output signal.
Each inverter INV2.about.INVn-1 is identically constituted to the first inverter INV1, and thus each input terminal is connected to an output terminal of a preceding inverter, and each output terminal is connected to an input terminal of a succeeding inverter.
In addition, the n-th inverter INVn is identically constituted to the first inverter INV 1. Thus, an output signal from a preceding inverter INVn-1 is inputted to its input terminal, and an input data DATAIN is outputted from its output terminal.
The operation of the thusly-constituted input buffer circuit will now be described with reference to FIGS. 2A-2D.
First, when the data signal DIN as shown in FIG. 2A and the low-level control signal WECS as shown in FIG. 2B are inputted, if a low external power voltage VCCL is applied to the input buffer circuit at the inverters'respective VCC terminals, the data signal DIN is delayed by the delay unit 1, and thus outputted as the input data DATAIN as shown in FIG. 2C.
On the other hand, when the data signal DIN as shown in FIG. 2A and the low-level control signal WECS as shown in FIG. 2B are inputted, if a high external power voltage VCCH is applied to the input buffer circuit at the inverters'respective VCC terminals, the data signal DIN is delayed by the delay unit 1, and thus outputted as the input data DATAIN as shown in FIG. 2D.
As illustrated in FIG. 2D, when the delay unit 1 is driven by the high external power voltage VCCH, not the low external power voltage VCCL, a driving current is increased as much as the external power voltage VCC rises. Thus each inverter INV1.about.INVn operates rapidly. Accordingly, a delay rate is lowered.
When the conventional input buffer circuit 5 is operated by the high external power voltage VCCH during a write operation, one must add more inverters in order to obtain a sufficiently long data hold time. However, when the low external power voltage VCCL is applied, the conventional input buffer circuit is delayed due to the additional inverters. Thus its operational speed becomes slower.
Also, when the delay unit 1 is operated by the high external power voltage VCCH, the driving current is increased.